Phase lock detector.

摘要

A phase lock detector for a digital phase locked loop frequency synthesiser in which phase errors, represented by phase error pulses of a duration equal to the relative time displacement of synthesised and reference waveforms in the phase locked loop, are compared with a predetermined time interval representing the maximum phase error acceptable in a phase-lock condition. A favourable result of the comparison may be required to persist for a predetermined time before a phase-lock indication is given, to avoid jitter or flicker of that indication in a near-lock situation.