| 摘要 |
The invention relates to an arrangement for verifying the correct functioning of memory locations of a read/write memory (4a and 4b) in a computer, the CPU (1) of which is connected to the read/write memory (4a and 4b) via a data and address bus (2, 3). To provide the possibility of a verification of the read/write memory (4a and 4b) of any complexity at any time and without time restriction independently of the process run and even during interrupt processing, a number of storage locations corresponding to the number of storage locations is made available in a physically separate read/write memory (4b and 4a) which is operated via the same data and address bus (2, 3) by the same CPU (1). These storage locations of the two read/write memories (4a and 4b) are selected by a common control logic (5) in such a manner that both storage areas can be used as separately addressable memories, of which one storage area is optionally used as working memory whilst the other storage area is subjected to a verification program. In this arrangement, the write operations of the continuously presented process data occur in parallel in both memory areas between the alternations of the two memory areas for work and test purposes following one another in time. However, read operations only occur from the memory area which is currently being used as working memory, until all data have been transferred from the memory area used in each case as working memory into the tested memory area by reading-out and writing-back the entire working memory volume with the aid of the CPU (1). |
