| 摘要 |
<p>PURPOSE:To obtain a control signal processing circuit capable of preventing the generation of malfunction and improving the reliability of a system by using a signal from a clock signal source as an internal clock signal and matching the phase of the internal clock signal with that of a clock signal from a CPU. CONSTITUTION:An original clock signal oscillated from an oscillator 3 is supplied to the CPU 1 as a system clock signal through a noise filter 6 arranged outside an ASIC 2 and supplied also to respective delays 11 to 1n arranged in the ASIC 2. A selection signal is outputted from the CPU 1 to a selector 4 and a delay matched with the selection signal out of the 1st to N-th delays 11 to 1n is selected. Since the selection signal is outputted from the CPU 1 so as to select a proper delay, the phase of the internal clock signal from the ASIC 2 can be matched with that of the clock signal from the CPU 1 and the malfunction of the system due to a phase deviation can be prevented.</p> |
