| 摘要 |
<p>PURPOSE:To reduce a circuitry so as to reduce power consumption by turning off NMOS transisters Trs when common address signals are in non-selection mode and turning on PMOS transisters Trs to make NMOST source high potential. CONSTITUTION:When common address signals A5 to A8 become a selection mode, all of NMOS Trs Q1 to Q4 are turned on and also all of PMOS Trs Q5 to Q8 are turned off. Then, the source of an NMOS Tr Qb becomes a low potential and when a signal A1 becomes a selection mode, the Tr Qb outputs a selection signal S1 to the gate of a Tr Qc to open the gate. A current is not allowed to flow from a high potential power source voltage Vcc to a low potential power source voltage Vss via a CMOS Tr1 during a time when the signal S1 is outputted because either of PMOS Tr Qa and Tr Qb in the Tr1 is in an off-state. Moreover, since this device is small in the scale as a decoder circuit, when a selection signal is wanted to be increased, the parallel connection of plural CMOS Trs with the Tr1 is especially effective.</p> |
