| 摘要 |
PURPOSE:To provide a clock synchronism controller capable of reducing signals to be used for synchronism between plural units. CONSTITUTION:A clock synchronism control circuit for an information processor provided with a 1st unit 110 for dividing the frequency of an original clock signal and obtaining an internal clock signal and at least one 2nd unit 120, the 1st unit 110 is provided with a 1st frequency dividing means 111 for dividing the frequency of an original clock signal and generating an internal clock signal, a synchronizing signal generating means 112 for receiving a scanning command input and generating a synchronizing signal indicating the start and end timing of a scanning mode by the change of a logical state synchronized with the internal clock signal and a 1st suppressing means 113 for suppressing the internal clock signal in accordance with the logical state of the synchronizing signal and the 2nd unit 120 is provided with a 2nd frequency dividing means 121 for generating an internal clock signal from the original clock signal in accordance with the synchronizing signal and a 2nd suppressing means 122 for suppressing the internal clock signal in accordance with the synchronizing signal. |
