发明名称 |
System for connecting plurality of electronic units to data and clock buses wherein transmitting and receiving data in synchronization with transmitting and receiving clock signals |
摘要 |
A data processing apparatus, including a number of electronic circuit units, in which high-speed data can be transmitted among the electronic circuit units. When data is transmitted from one electronic circuit unit to another electronic circuit unit, a clock signal to fetch the data in the sink side electronic circuit unit is transmitted from the source side electronic circuit unit via a clock signal line having the same signal propagation delay characteristics as those of the data signal line.
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申请公布号 |
US5452436(A) |
申请公布日期 |
1995.09.19 |
申请号 |
US19950367927 |
申请日期 |
1995.01.03 |
申请人 |
HITACHI, LTD. |
发明人 |
ARAI, KIYOKAZU;YAMAGIWA, AKIRA;OKABE, TOSHIHIRO |
分类号 |
G06F13/42;G06F1/10;G06F13/00;H04L7/00;H04L12/40;(IPC1-7):G06F1/04 |
主分类号 |
G06F13/42 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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