Digital signal multiplexing apparatus and demultiplexing apparatus.

摘要

The multiplexer comprises n (an arbitrary integer) multiplexing circuits (11 to 1n) that converts signals input from multiple circuits into m (an arbitrary integer) parallel signals having a first .. transmission speed to which an additional bit is added, a `parallel-serial converter circuit (40) and buses (30) that connect n multiplexing circuits and the parallel-serial convert circuit together. Each of the n multiplexing circuits has a circuit that successively sends the m parallel signals onto the buses using pulse signals of a second transmission speed which is n times as fast as the first transmission speed. A digital signal separator comprises a serial parallel converter circuit (75), n (an arbitrary integer) separating circuits (51 to 5n) that separate the additional bit from the m parallel signals of the serial parallel converter circuit (75) and sends the signals onto circuits at a predetermined speed, and buses that connect the serial-parallel converter circuit (75) and the n separating circuits together. Each of the separating circuits receives signals from the serial parallel converter circuit sent onto the buses at a clock timing of the same speed as the predetermined tranmissionn speed. @(58pp Dwg.No.3/19)@.