| 摘要 |
PURPOSE:To rapidly and surely perform the initialization and the restart operation of a phase locked loop circuit by providing a means which performs the prescribed initialization of each clock frequency division circuit by detecting the generation and the recovery of a fault in a clock signal. CONSTITUTION:A write clock frequency division circuit 1 performs the (n)- frequency division of a write clock signal ClKw, and outputs (n) write pulses Pw1-Pwn having phase differences corresponding to each one clock cycle sequentially. A readout clock generating means 100 generates a readout clock signal ClKr asynchronous to the signal ClKw, and a readout clock frequency division circuit 3 performs the (n)-frequency division of the signal, and outputs readout pulses Pr1-Prn having the phase differences corresponding to each one clock cycle sequentially. A memory 2 stores serial binary input data d1 synchronized with the signal Clkw in an area designated by the write pulse bit by bit, and outputs the content of one bit in the area designated by the readout pulse sequentially as readout data d0. An initialization means 200 detects the generation and the recovery of the abnormality in the signal ClKw by the signal ClKr, and performs the initialization by synchronizing the circuit 1 with the signal ClKw and the circuit 3 with the signal Clkr. |
