发明名称 |
Decoder circuit for generating a system clock signal phase locked to a range tone signal |
摘要 |
A decoder circuit for receiving a video input signal which includes Manchester coded data bits and a range tone component having a frequency of about 102.6 kilohertz. A phase lock loop circuit detects the presence of the 102.6 kilohertz range tone component and then generates a system clock signal which is phase locked to the range tone component of the video input signal. The system clock signal is provided to a clock generating circuit which generates a clock signal having four phases. The phase lock loop circuit also provides a logic signal which is supplied to a data detecting circuit allowing the data detecting circuit to convert the Manchester coded data bits to digital data bits.
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申请公布号 |
US5450136(A) |
申请公布日期 |
1995.09.12 |
申请号 |
US19940242399 |
申请日期 |
1994.05.13 |
申请人 |
THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE NAVY |
发明人 |
CIRINEO, ANTHONY |
分类号 |
H04N7/00;H04N7/56;(IPC1-7):H04N17/00;H04N9/45 |
主分类号 |
H04N7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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