| 摘要 |
PURPOSE:To provide a scanning circuit capable of dealing with a liquid crystal display with a large area and high resolution and a contact type image sensor by remarkably reducing a clock signal delay. CONSTITUTION:This scanning circuit is constituted of single phase clock control type inverters 101 and 111 delay-transferring a signal from the prestage to the succeeding stage while being controlled by a clock signal (phi), two inputs logical gate circuits (NOR in an odd numbered stage, NAND in an even numbered stage) to which the output signals and the clock signal (phi) are supplied, and output buffer circuits 20 and 21 outputting the outputs of these logical gate circuits 1-2 and 112 as scanning pulse signals. The output signal of a (2N-1)-th stage is outputted delayed by one period of the clock signal (phi) for an input signal, and the output signal of a 2N-th stage is outputted delayed by one period of the clock signal (phi) for the output signal of the (2N-1)-th stage, and further, the output signal of the (2N-1)-th stage is outputted synchronizing with the timing of the fall of the clock signal (phi), and the output signal of the 2N the stage is outputted synchronizing with the timing of the rise of the clock signal (phi). |
