发明名称 SIMD architecture with transfer register or value source circuitry connected to bus
摘要 A SIMD parallel processor includes two types of circuitry interconnecting its processing units: One kind interconnects the processing units into an array so that each processing unit can transfer data to an adjacent processing unit in the array and can receive data from an adjacent processing unit; the processing units can, for example, be interconnected in a one-dimensional array. Another kind of interconnecting circuitry includes bus circuitry to permit greater freedom in transferring data to and from processing units. Connected to the bus is a register, so that data can be transferred between processing units by first transferring data from one processing unit to the register and by then transferring data from the register to another processing unit. Or data stored in the register can be sent to a subset or to all of the processing units. Similarly, control circuitry can itself provide data on the bus for transfer to one, a subset, or all of the processing units. A bidirectional register can be connected between each processing unit and the bus, so that a processing unit can be selected to provide data to the bus by selecting its bidirectional register. Similarly, each processing unit can include a memory that can be selected with a write enable signal so that a set of processing units can be selected to receive and store in memory data from the bus.
申请公布号 US5450603(A) 申请公布日期 1995.09.12
申请号 US19920993218 申请日期 1992.12.18
申请人 XEROX CORPORATION 发明人 DAVIES, DANIEL
分类号 G06F9/38;G06F13/38;G06F15/16;G06F15/173;G06F15/80;(IPC1-7):G06F13/00 主分类号 G06F9/38
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