发明名称 DATA PROCESSOR
摘要 PURPOSE:To unnecessitate a complicated circuit to be added to a decoder and to display a partially processed image in real time at the time of mosaic processing by invalidating only the amount of data corresponding to an instruction on the high frequency component side of a data block to which discrete cosine transformation is executed. CONSTITUTION:At a multimedia international standardizing system circuit 12, the bit sequence of animation image data and the bit sequence of voice data are separately extracted from the regenerative signals of a medium 11, the bit sequence of animation image data is outputted to a reception buffer 13, and the bit sequence of voice data is outputted to an audio circuit 14. At the buffer 13, the bit sequence of animation image data from the circuit 12 is received, and this is transmitted to a buffered variable length encoding decoder 15. At the circuit 14, audio signals are outputted from a speaker not shown in the figure by performing D/A conversion processing based on the bit sequence of voice data. Thus, when a regenerative image is a bidirectional picture, images under decoding at present are added by an adder 22 but when it is an in-frame or inter-frame image, the images are outputted as they are, and the order of image is made correct.
申请公布号 JPH07240919(A) 申请公布日期 1995.09.12
申请号 JP19940029332 申请日期 1994.02.28
申请人 TOSHIBA CORP 发明人 KUMA YAKUSHI
分类号 H04N5/262;G06T5/00;G06T9/00;H04N1/41;H04N5/92;H04N19/102;H04N19/119;H04N19/132;H04N19/134;H04N19/136;H04N19/159;H04N19/172;H04N19/174;H04N19/176;H04N19/177;H04N19/18;H04N19/186;H04N19/189;H04N19/196;H04N19/30;H04N19/42;H04N19/423;H04N19/503;H04N19/51;H04N19/523;H04N19/527;H04N19/573;H04N19/577;H04N19/587;H04N19/593;H04N19/60;H04N19/61;H04N19/625;H04N19/85;H04N19/91 主分类号 H04N5/262
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