| 摘要 |
For switching data time slots between input and output data signals, each having a multiframe structure, a time slot switching device comprises only one time slot switching circuit. Consequently, the device comprises a sole data memory, a single novel write address generator, and only one novel read address generator. The write address generator comprises first through N-th frame synchronization units, where N represents the number of attributes by which the data time slots are featured. Connected to the frame synchronization units, a selector is controlled by a switch mode memory (SWM) controlled, in turn, by a central processing unit. Like each conventional read address generator, the novel read address generator comprises an address control memory (ACM) controlled by the central processing unit. Only one phase adjusting circuit is used to adjust operation of the read address generator relative to that of the write address generator as regards phases of operation.
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