Process for manufacturing semi-conducteur device with planarized surface and application to the manufacturing of bipolar transistors and DRAM.

摘要

On the surface of a semiconductor layer structure (1) which has elevations (2) up to a maximum step height, an insulating layer (4), the thickness of which is greater than the maximum step height, is applied. The insulating layer (4) is structured such that it has uneven zones (7) having essentially the same lateral extent in the region of the edges of the elevations (2). The uneven zones (7) are planarised by chemical/mechanical polishing and/or deposition, flow-out and etching-back of a planarisation layer.