发明名称 SIGNAL COMPANDING CIRCUIT
摘要 <p>PURPOSE:To ensure the reproduction with complementary expansion factor to the compressibility to prevent the S/N deterioration caused by the noise, by piling the high frequency signal outside the band onto the right and left tracks at the recording time and recording the information of the companding factor. CONSTITUTION:The compressibility is determined in accordance with the output of companding factor adjusting circuit 14 for the right signal used for the stereo via variabl egain amplifier circuit VCA11 controlled by level sensor 12 and 13 as well as for the felt signal via VCA16 controlled by level sensor 17 and 18. After this, the signal given from high frequency signal generator circuit 19 is piled on each output with phase difference phi(C2). Thus, each signal is recorded on the stereo right and left tracks of tape recorder 21. Both the right-left signals and high frequency signals are extracted respectively via LPF 22 and 23 HPF32 and 33, and the level sensors are conrolled by the comparison output of the high frequency signal featuring the phase difference. As a result, the right and left signals are obtained through VCA24 and 25 with the expansion factor complementary to the compressibility.</p>
申请公布号 JPS5459809(A) 申请公布日期 1979.05.14
申请号 JP19770126973 申请日期 1977.10.20
申请人 SANYO ELECTRIC CO 发明人 NISHIMURA MASARU
分类号 G11B20/04;H03G7/00;H04B1/64;H04H40/72 主分类号 G11B20/04
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