SEMICONDUCTOR WELL GUARD RING METHOD

摘要

The semiconductor device having a second conductive type well resgions formed on a first conductive type substrate and a second conductive type well guard ring junction region formed surrounding the well region, includes: a first contact hole arranged in the first direction to expose the junction region; a first conductive ion implanting active region isolated by a channel region formed in the well region; a second contact hole arranged in the second direction to expose the active region region; a first conduction layer with which the first contact hole is filled, being extended in the second direction; a third contact hole formed by selectively etching an interlayer insulating film formed on the first conduction layer; and a second conduction layer in contact with the first conduction layer through the third contact hole and the active region through the second contact hole. The latch-up of CMOS circuit is effectively prevented without an increase of layout of semiconductor device.