发明名称 Synchronous DRAM having initial mode setting circuit
摘要 The initial mode setting circuit 30 has a circuit 31 for generating a reset pulse RST after detecting that the power source voltage VCC has reached a specified value when the power source voltage VCC starts up, and fuses 32 to 37, each one end of which is commonly connected to the output end of the reset signal generating circuit 31 and the other ends of which are connected to one of either the set input end S or the reset input end R of the flip flops 11 to 13. The fuses 32 to 37 are melted and cut off electrically or with a laser.
申请公布号 US5448528(A) 申请公布日期 1995.09.05
申请号 US19940307420 申请日期 1994.09.19
申请人 FUJITSU LIMITED 发明人 NAGAI, EIICHI
分类号 G11C11/401;G11C7/10;G11C11/407;G11C11/4096;(IPC1-7):G11C13/00 主分类号 G11C11/401
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