发明名称 Adapters with descriptor queue management capability
摘要 A processor stores descriptors without explicit linkages, in non-contiguous memory locations, and sequentially hands them off to an adaptor which manages scheduling and processing of data transfers defined by the descriptors. Each descriptor is handed off in a request signalling process in which the processor polls the availability of a request register in the adaptor, and writes the address of a respective descriptor to that register when it is available. The adapter then schedules processing of the descriptor whose address is in the request register. The adapter manages a "Channel Descriptor Table" (CDT), which defines the order of processing of descriptors designated by the requests. In effect, the CDT defines a linked list queue into which the adapter installs descriptors, in the sequence of receipt of respective requests. Using the CDT information, the adapter retrieves successively queued descriptors and controls performance of operations (data transfer or other) defined by them. Accordingly, descriptors in the queue are retrieved and respectively defined operations are performed, in the order of receipt of respective requests; as if the descriptors had been stored by the processor with explicit linking and chaining associations and handed off to the adapter as an explicitly chained set of descriptors. In a preferred embodiment, a "multichannel adapter unit" (MAU), directing data transfers relative to multiple channels, contains one request register for all channels and a separate CDT and "request address port" dedicated to each channel. Requests accompanied by addresses designating these ports are "funneled" through the request register to CDT queues of respective channels. The processor can effectively remove a descriptor from any CDT queue, without potentially compromising handling of data transfers defined by other descriptors in the queue, by writing a "skip code" to the descriptor. Upon retrieving a descriptor with a skip code, the adapter automatically skips the operation defined by that descriptor and chains to a next descriptor (if the queue defined by the CDT is not empty).
申请公布号 US5448702(A) 申请公布日期 1995.09.05
申请号 US19930024981 申请日期 1993.03.02
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 GARCIA, JR., SERAFIN J. E.;GATSON, MICHAEL S.;HOCH, GARY B.;STELZER, ERIC H.;WILLIAMS, DONALD G.
分类号 G06F13/12;G06F13/20;(IPC1-7):G06F3/00;G06F13/00 主分类号 G06F13/12
代理机构 代理人
主权项
地址