| 摘要 |
<p>PURPOSE:To suppress variation of erase characteristics by reducing the current between a source and a substrate by tunneling between bands at the time of erasing. CONSTITUTION:Two steps of erasing operation are conducted by a CHE/FN type NOR type flash EEPROM. Electrons in a floating gate-(FG) are drawn from a source by applying 10.5V, a threshold voltage is lowered to an intermediate level of about 3V. Subsequently, at the second step, the electrons in the FG are further drawn from the source by applying, for example 12V, and the threshold voltage is lowered to 1-2V. Accordingly, at the time of erasing, the current between the source and the substrate can be largely decreased by tunneling between bands. Thus, variation of a source potential of each memory cell via a source diffused resistor is suppressed, and variation of erase characteristics can be suppressed. The capability of a booster circuit is not marred, and it can be operated by a single power source.</p> |
