| 摘要 |
For interfacing a random-access (microprocessor-type) device to a sequential-access type device, such as EISA (Extended Industry Standard Architecture)-bus-memory (RAM) cell array (110), employed is a dual-port random-access-memory (RAM) cell array (110), for storing/retrieving words of data and a set of command and status registers (COMMAND/STATUS REGS) (160). Also employed is a combination of a set of end-address registers (END ADD #1-2) (162), a set of comparators (COMPARATOR) (164), and a set of next-address registers (NEXT ADD #1-2) (166), the combination permitting the sequential-access and random-access dual-port memory buffer (100) to jump from one dual-port random-access-memory (RAM) cell-array (110) sequential address, stored in an end address register (END ADD #1-2) (162) to another dual-port random-access-memory (RAM) cell-array (110) sequential address, stored in a next address register (NEXT ADD #1-2) (166). Further utilized is a combination of an incrementor (180) and a pointer register (182), the incrementor and pointer register combination providing the dual-port random-access-memory (RAM) cell array (110) a sequential address; a pointer-logic unit (200); and a semaphore circuit (202).
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