发明名称 Clock signal switching circuit
摘要 A clock signal switching circuit, to which at least first and second clock signals and a switching signal requesting a switching operation are inputted, and which selectively outputs one of the inputted first and second clock signals by the requested switching operation, the second clock signal being synchronized with the first clock signal and having an integer multiple times cycle of the first clock signal, is provided with: a generating device, to which the second clock signal is inputted, for generating a strobe pulse at a transition timing of the inputted second clock signal; and a sampling device, to which the switching signal and the generated strobe pulse are inputted, for sampling the inputted switching signal at a timing of the inputted generated strobe pulse. The clock signal switching circuit is also provided with: a switching device, to which the first and second clock signals and the sampled switching signal are inputted, for switching to output one of the inputted first and second clock signals in correspondence with the inputted sampled switching signal.
申请公布号 US5448597(A) 申请公布日期 1995.09.05
申请号 US19940235134 申请日期 1994.04.28
申请人 SHARP KABUSHIKI KAISHA 发明人 HASHIMOTO, YOSHINORI
分类号 G06F1/06;H03K5/00;H03K5/135;H04L7/00;(IPC1-7):H04L7/00 主分类号 G06F1/06
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