发明名称 Multiplication operational circuit device
摘要 An operational circuit device for calculating a plurality of bit data includes, an input unit for inputting a plurality of bit data, a constant current source provided for each of the plurality of bit data for generating a predetermined current in accordance with the bit data inputted from the input unit and a calculation unit for calculating a sum of the predetermined currents from the constant current sources.
申请公布号 US5448506(A) 申请公布日期 1995.09.05
申请号 US19940221449 申请日期 1994.04.01
申请人 CANON KABUSHIKI KAISHA 发明人 TATENO, TETSUYA
分类号 G06G7/14;G06J1/00;(IPC1-7):G06J1/00 主分类号 G06G7/14
代理机构 代理人
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