| 摘要 |
<p>PURPOSE:To decrease the circuit scale of a DCT processor. CONSTITUTION:The output of a butterfly arithmetic unit is inputted to a product sum arithmetic unit 300 in a forward DCT while the output of the product sum arithmetic unit 300 is inputted to the butterfly arithmetic unit in a backward DCT, respectively. The product sum arithmetic unit 300 employs register circuits 70 and 80, consisting of eight bit shift registers 71 to 74, and 81 to 84 which have 16-bit parallel input and 2-bit shift outputs and differ in it width, as bit array distribution circuits; and data are inputted in order from the bit shift register 71 which is long in bit width and shifted in the respective bit registers to the right by two bits in each cycle. Further, the bit array is inputted to eight ROM/accumulators(RAC) 171-178 of a ROM/accumulating circuit 170 while shifted, cycle by cycle, to output final accumulation results in proper order by providing four shift registers 130-160 between the register circuits 70 and 80 and ROM/accumulating circuit 170.</p> |
