Fast-packet switching networks.

摘要

A modular architecture for fast-packet networks that comprises line interface devices (LIDS) exchangeable to support numerous line interfaces. The LIDs supply frame relay packet management devices (FRYPAMs) with unified framed data in HDLC format and clock signals. The receiving FRYPAMs perform CRC checking, check look-up tables to convert the DLCI fields if needed, write the received frames with correct FCS fields into a frame buffer RAM and communicate with other FRYPAMs to update transmission queues. The transmitting FRYPAMs read the frames from the frame buffer RAM and send them to the transmitting LIDs coupled to destination end points. The transmitting LIDs convert the HDLC data from the FRYPAMs to the format appropriate for the specific line interface and transmit the information to the destination end points. A frame buffer manager allocates available frame buffers in the frame buffer RAM among the FRYPAMs. A control and maintenance processor handles control and maintenance operations for the fast-packet network. It updates the look-up tables and communicates DLCI and line interface parameters to the LIDs in real time.