SERIAL DATA RECEIVING APPARATUS

摘要

This serial data receiving apparatus is intended to realize the receiving process of serial data having an inferior SN ratio with a simple arrangement and at low cost. A one-bit length of the serial data is divided into several blocks. The sampling data is input at multiple points of each block by using a shift register built in a microcomputer. The data is temporarily held so that the data at the same number block of each block is accumulated for several bits. The accumulation of the data results in cancelling the noise components and leaving the original signal components. This overlapping type receiving system makes it possible to clarify the receiving phase of a preamble signal for bit synchronization and to establish the bit synchronization. Next, the sampling data signals are entered at the multiple points based on the resulting receiving timing and the logic value of the bit is determined according to the ratio of the number of values of "1" to "0" contained in the data. Further, by using the reversal symmetry of the first half and the second half of the bi-phase codes, it is possible to realize the methods for establishing bit synchronization and determining a logic bit more effectively and accurately.