A parallel-plate plasma etching apparatus includes a susceptor electrode and a shower electrode which are arranged in a process chamber. A semiconductor wafer is placed on the susceptor electrode. A shower region defined by a plurality of process gas supply holes is formed in the shower electrode. The shower electrode is cooled by a cooling block and causes an effective electrode portion of the shower electrode to have a temperature gradient such that a temperature at the central portion of the effective electrode portion is lower than a temperature at the peripheral portion of the effective electrode portion. The diameter of the shower region is selected to be smaller than the diameter of the wafer by 5 to 25% such that degradation of planar uniformity of a degree of etching anisotropy on the wafer caused by the temperature gradient of the effective electrode portion is compensated for. The diameter of the effective electrode portion is selected to be larger than the size of a wafer by 5 to 35% such that a taper angle of a side wall to be etched formed by etching is set to be 85 DEG to 90 DEG .
申请公布号
US5445709(A)
申请公布日期
1995.08.29
申请号
US19930154566
申请日期
1993.11.19
申请人
HITACHI, LTD.;TOKYO ELECTRON LIMITED;TOKYO ELECTRON YAMANASHI LIMITED