| 摘要 |
PURPOSE:To reduce a silicide forming area for the continuity between a dual gate structure p-type impurity area and an n-type impurity area by providing the manufacture of a semiconductor device comprising a complementary field effect transistor. CONSTITUTION:The silicide forming area on a semiconductor layer 9 formed of silicon is covered with an oxidation-resistant side wall 12 formed by self- alignment, separately implant p-type and n-type impurities by using the oxidation-resistant side wall 12 as a part of a mask, and dual gate patterns 16 and 17 are formed by patterning the semiconductor layer 9. Then, the surfaces of the dual gate patterns 16 and 17 are oxidized using the oxidation- resistant side wall 12 as a mask, and the exposing surface of the semiconductor layer 9 is silicified by selectively removing the oxidation-resistant side wall 12. |
