CMOS power-on reset circuit

摘要

A CMOS power-on reset circuit has a delay capacitor to provide a predetermined delay period. Charging and discharging of the delay capacitor is controlled by the state of a flipflop circuit. An input comparator monitors a power supply input voltage. An invalid input voltage level immediately changes the reset output signal to the invalid state and discharges the capacitor. Even after the input voltage has recovered to a valid level, recharging the capacitor is delayed until the capacitor has substantially discharged, thereby ensuring at least a predetermined delay period after the last fault condition. The reset output signal is coupled in a feedback configuration so as to lower the threshold voltage when the reset output switches to the valid state, to allow limited power supply sag, for example due to motor start-up, without resetting the circuit. Multiple power supply voltages are continuously monitored in a CMOS integrated configuration by additional input scaling resistor networks and input comparators, all coupled to the common 2-level threshold voltage node.