| 摘要 |
<p>PURPOSE:To prevent the efficiency of arithmetic such as FFT arithmetic by an arithmetic processor from decreasing due to variation of the transfer speed and delay quantity of input data. CONSTITUTION:When an arithmetic processor performs the arithmetic processing such as FFT for respective data sets 105 consisting of data 104 of K successive samples, it is supposed that the number of data processed by the arithmetic processor in each unit time is N times as large as the number of data inputted by a shift register part 101 in each unit time. In this case, a data set which is shifted in segmentation start position in a data sequence by K/N samples is transferred from the shift register part 101 to a buffer register part 102 each time the arithmetic processor completes preparations for arithmetic for a new data set, and the data set is inputted to the arithmetic processor through an output data selection control part 103.</p> |
