Address decoder with memory wait state circuit.

摘要

The electronic postage meter control system includes a printing unit which is responsive to control signals from a control circuit. The control circuit includes a programmable microprocessor (13) in bus communication with memory units (NVM1-3) for accounting for the postage printed by the printing means. The microprocessor (13) is also in bus communication with an application specific integrated circuit (15). The integrated circuit has an address decoding module (28) for generating a unique combination of control signals in response to a respective address placed on the bus by the microprocessor (13). Memory units (NVM1-3) are responsive to a chip select control signal to enable writing to the respective memory units (NVM1-3). The integrated circuit also includes a non-volatile memory access delay circuit for causing the chip select signal from the address decoding module enabling those memory units requiring additional access time to stay active for the additional time.