| 摘要 |
in a write per bit mode where external input data is selectively written in internal cells, a zero-th write per bit mode and input data detecting portion and an i-th write per bit mode and input data detection portion for inputting buffered signals from external input signals and input data to generate selectively masked write enable signals, respectively; and a zero-th data input buffer to an i-th data input buffer for inputting the write data enable signals and input data, to thereby generate internal write data, respectively.
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