INTERRUPT PROCESSING UNIT IN DATA PROCESS DEVICE

摘要

The device provides an enhanced hardware interrupt handling method for the microcontroller. The device comprises a pending register for receiving the interrupt request signal and maintaining the data; an interrupt request register for generating the interrupt request signal to CPU; a vector address generator for generating the vector address to CPU; a combinational logic unit for detecting the loading of the vector address to CPU by using the interrupt acknowledgement and vector read(VR) signal; and an interrupt disable signal generator for generating the pending register reset signal.