发明名称 METHOD AND APPARATUS FOR SINGLE CYCLE CACHE ACCESS ON DOUBLE WORD BOUNDARY CROSS
摘要 A cache memory system and method control a random access read/write cache memory (122) that stores a plurality of cache data lines (148). The bytes in each cache data line (148) correspond to bytes stored in sequential addresses in a main memory (104). The cache memory (122) is organized to provide storage of a plurality of double words in each cache data line (148). To retain main memory consistency, input circuitry receives and aligns data before storage in the cache memory (122). A separate instruction output path (114) provides access to a plurality of double words in a single cycle. A separate data output path (112) provides access to data that crosses a double word boundary in a single cycle and provides the data as aligned data.
申请公布号 WO9522791(A2) 申请公布日期 1995.08.24
申请号 WO1995US01779 申请日期 1995.02.08
申请人 MERIDIAN SEMICONDUCTOR, INC. 发明人 WHITTED, GRAHAM, B., III;KANE, JAMES, A.;CHANG, HSIAO-SHIH
分类号 G06F12/08 主分类号 G06F12/08
代理机构 代理人
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