发明名称 CLOCK SYNCHRONOUS CIRCUIT
摘要 PURPOSE:To obtain a simple and cheap circuit, by composing two exclusive-OR circuits of one discriminator, delay line, LPF, and voltage control oscillator. CONSTITUTION:Exclusive-OR circuit 22 phase-compared signals (d), (i) and (m) discriminated 20 and regenerated by output (regenerative clock) signal (C) of voltage control oscillator 16 with output signal (e) delayed 21 by T/2, thereby obtaining output waveforms (f), (j) and (n). Then, the 2nd phase comparison between the output signal of circuit 22, and regenerative clock signals (c), (h) and (l) having passed through delay line 21' with the same delay time as circuit 22 is done by exclusive OR circuit 22', thereby obtaining pulse strings (g), (k) and (o) whose duty ratios are 50%, more than 50%, and less than 50% when phases coincide, delay and advance. Next, those signals are integrated by LPF15 to obtain zero, positive and negative voltages and the phase of oscillator 16 is controlled corresponding to the positive and negative voltage, so that when phases synchronize, the system will become stable.
申请公布号 JPS5466062(A) 申请公布日期 1979.05.28
申请号 JP19770132503 申请日期 1977.11.07
申请人 NIPPON TELEGRAPH & TELEPHONE 发明人 SAITOU YOUICHI;HORIKAWA IZUMI
分类号 H03L7/08;H03K5/00;H04L7/033 主分类号 H03L7/08
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