| 摘要 |
Disclosed here is a delaying detection circuit which is employed for reproducing a digital signal from a received signal and has a constitution in which a present input signal is multiplied with an input signal before one symbol time. The delaying detection circuit according to this invention has a constitution including a plurality of delaying circuits which delays an input signal by respectively different delay times and a synthesis circuit which estimates an input signal before one symbol time based on output signals of these delaying circuits so as not to produce errors in a demodulated data even when one symbol time is not an integer multiple of a period of a carrier wave. |
