发明名称 PARALLEL SERIAL CONVERSION DEVICE AND LINEAR CONVERSION DEVICE USING THIS
摘要 <p>PURPOSE:To reduce an occupancy area as small as possible by uniting two orthogonal memories. CONSTITUTION:When a decode signal in which a first memory cell 1 of some memory cell block column is selected, is inputted to a second word line selecting means, a word line for reading is selected. Then, data is read out from a first memory cell of each pair of memory of a memory cell block selected by the selected word line to a corresponding data read-out bit line. Parallel serial conversion is performed by reading out data from the first memory cell of each pair of memory cell of a residual memory cell block column in the same way. Since a first word line selecting means, a data input bit line, and second word lines for writing WA1, WB1 are not used during this read-out operation, data can be written in a second memory cell 3 in a memory cell block of a row using these lines and the like. Thereby, parallel serial conversion can be performed without interruption, and a occupancy area can be reduced.</p>
申请公布号 JPH07226082(A) 申请公布日期 1995.08.22
申请号 JP19940015218 申请日期 1994.02.09
申请人 TOSHIBA CORP 发明人 NAGAMATSU TORU;MATSUI MASAKI
分类号 G11C11/41;G06F17/10;G06F17/14;G11C8/12;H03M9/00;(IPC1-7):G11C11/41 主分类号 G11C11/41
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