发明名称 Elastic store memory circuit
摘要 An elastic store memory circuit includes first and second elastic store memories. Each of the first and second elastic store memories generates a phase comparison signal when a phase difference between a write timing and a read timing is within a predetermined phase range. The elastic store memory circuit also includes a selector which selects either the input data read out from the first elastic store memory or the input data read out from the second elastic store memory, and a slip signal generator for generating a slip signal on the basis of a write reset timing at which the first and second elastic store memories are reset, a read reset timing at which the first and second elastic store memories are reset, and the phase comparison signal. The slip signal indicates which one of the write reset timing and the read reset timing precedes the other one.
申请公布号 US5444658(A) 申请公布日期 1995.08.22
申请号 US19940206221 申请日期 1994.03.07
申请人 FUJITSU LIMITED 发明人 IZAWA, NAOYUKI;ASO, YASUHIRO;UCHIDA, YOSHIHIRO;KAKUMA, SATOSHI
分类号 H04J3/06;H04L7/00;(IPC1-7):G11C7/00 主分类号 H04J3/06
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