| 摘要 |
An interface circuit for linking microprocessors, intended to limit the current (Iout) in the link (L1-L2) by inserting in the link the emitter-collector path of a first transistor (T1) which is in the saturated state during operation. This circuit includes a second transistor (T2) which has a geometry k times smaller than that of the first transistor (T1) and which is coupled to the first transistor (T1) so as to produce a copy (Iy) of the link current (Iout), and a base current generator (10) which produces an output current (Iz) which feeds the bases of the first and the second transistor (T1, T2), and which is a regressive function of the copy current (Iy), on the basis of a fixed reference current (I0). A pair of transistors (T3, T4), similar to the first and the second transistor (T1, T2) but connected to the link (L1-L2) in an inverted manner, provides protection for bidirectional operation. The interface circuit can be used for temporary links between different microprocessors, for example in chip cards.
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