发明名称 MANUFACTURE METHOD OF SEMICONDUCTOR ELEMENT CONTAINING PACKAGE
摘要 PURPOSE:To provide a manufacturing method of semiconductor containing package capable of simultaneously bond plating metallic layers in even thickness on the sides of outer lead pins for bringing respective outer lead pins into excel lent electrical contact with any outer electric circuit without fail. CONSTITUTION:A plating jig A comprising a planar metallic body 10 having holes 11 for inserting lead pins 7 and the semiconductor element containing package having notches 9 on the sides near the ends of the outer lead pins 7 are to be prepared. Next, the sides between the ends of the outer lead pins 7 and the notches 9 are made adhere to the holes 11 of the plating jig A and then the whole surface of the outer lead pins 7 is simultaneously coated with plating metallic layers 8. Finally, the outer lead pins 7 are drawn out of the holes 11 of the plating jig A to be cut off at the notches 9 for removing the ends of the outer lead pins 7.
申请公布号 JPH07226451(A) 申请公布日期 1995.08.22
申请号 JP19940017083 申请日期 1994.02.14
申请人 KYOCERA CORP 发明人 HOSOI YOSHIHIRO
分类号 H01L23/12;H01L23/04 主分类号 H01L23/12
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