| 摘要 |
PURPOSE:To eliminate an undesired hazard from data including hazard by providing FFs that receives a clock signal and data including hazard and obtains Q output data and a hazard eliminating section ANDing the Q output data and an output of an n-stage FF to the circuit. CONSTITUTION:Output data ALM1-ALM3 being Q outputs of FFs 14-16 are given respectively to a hazard eliminating section comprising an N-stage FF 17 and an AND circuit 18. Then the AND circuit 18 ANDs output data shifted by an N-stage in the FF 17 and the output data ALM1-ALM3 from the FFs 14-16 without any processing The &number N of stages of the FF 17 shifting the data ALM1-ALM3 is decided optionally. Furthermore, an input clock signal CLK is used for a clock signal to the FF 17 of the hazard eliminating section comprising the FF 17 and the AND circuit 18 without any modification. As a result, when a random short-time hazard is intruded on the data ALM1-ALM3 and an undesired pulse is caused in the output of the FFs 14, 17, the undesired pulse is eliminated at an output ALM 4 of the circuit 18 of the hazard eliminating section and correct output data are obtained. |
