发明名称 RESULT NORMALIZATION MECHANISM AND METHOD OF OPERATION
摘要 PURPOSE: To provide a result normalization mechanism which generates a mask for showing the position of '1' at the head in an adder result in two stages and which is used together with an adder. CONSTITUTION: In the first stage, a head '0' prediction mechanism decides the position in two digits. In the second stage, a head '0' count indicator decides the position to a single digit. The number of digits by which the respective stages of a multiplexer array shift the adder result is controlled by using the mask. Thus, '1' at the head is contained in the output of the multiplexer array. The result normalization mechanism can effectively be used in a high performance application field in a floating point execution unit in a data processor and in a digital signal processing system.
申请公布号 JPH07225671(A) 申请公布日期 1995.08.22
申请号 JP19940300015 申请日期 1994.12.02
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 BURATSUDORII JII BAAJIESU;TEIMOSHII EI ERIOTSUTO;KURISUTOFUAA EICHI ORUSON;TERENSU EMU POTSUTAA
分类号 G06F7/485;G06F5/01;G06F7/00;G06F7/50;G06F7/76 主分类号 G06F7/485
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