| 摘要 |
PURPOSE:To allow a system clock to phase-lock to a horizontal synchronizing signal including skew in a short period. CONSTITUTION:This circuit is composed of a synchronizing separator circuit section 1 applying synchronization separation to a video signal to extract a horizontal synchronizing signal, a synthesis section 2 generating an additional horizontal synchronizing signal being the synthesis of added H pulses, an edge detection section 8 detecting a horizontal synchronizing signal and outputting a pulse train of the horizontal synchronizing signal formed whose pulse width is equal to a clock pulse width, a skew detection section 7 detecting skew based on the pulse train and generating a skew pulse or an added H pulse, a phase difference detection section 3 having a 1st input and a 2nd input inputting the output of the synthesis section 2, an LPF 4 converting an output signal based on the phase difference into a DC voltage, a VCO 5 receiving the control of an oscillated frequency through the control input and a frequency divider 6 frequency-dividing the system clock to feed back it to a 2nd input of the phase difference detection section 3. |
