| 摘要 |
PURPOSE:To prevent a phase of a recovered clock signal from being deviated from a phase of a digital orthogonal modulation signal received by an A/D converter circuit even when the circuit charactereistic is changed due to a temperature change or a secular change or the like and to facilitate large scale integration of the circuit by adopting digital signal processing, to miniaturize a receiver and to reduce its cost. CONSTITUTION:Every time I and Q signal data obtained by applying A/D conversion to I and Q signals obtained through orthogonal demodulation at a frequency being four times the symbol rate are inputted, a square sum signal data generating circuit 2a fetches the data to calculate a square sum, and a phase error signal data generating circuit 3a calculates a difference between the square sum signal data this time obtained through the arithmetic operation square sum signal data of the last but one to generate phase error signal data, which are outputted. |
