SEMICONDUCTOR MEMORY DEVICE WITH THE CIRCUIT OF REFRESH-SHORTENED IN DATA RETENSION MODE

摘要

a refresh cycle controller(1) for controlling the frequency of refresh cycles in data retention mode based on at least one row address bit and a self-refresh signal; a word line boosting level generator(2) for increasing a boosting level of the word lines to the memory in data retention mode in response to the self-refresh signal and a clock-enable signal; and a memory(3) for supplying a signal input from word line boosting level generator(2) to the word line selected by the refresh cycle controller(1).