MEMORY CIRCUIT FOR COLUMN DECODER PROCESSING

摘要

The memory circuit for processing column decoder comprises a memory cell array in which information is stored; a bit line sense amplifying unit for amplifying the data of the selected memory cell array; a row address buffer unit for amplifying the address input via an address input terminal to a row address; a predecoder for predecoding the row address applied from the row address buffer unit; a row decoder for decoding the row address applied from the predecoder to select the word line of the memory cell array; a column address buffer unit for amplifying the address input via the address input terminal to a column address; an address change detection signal generator for generating an address change detection signal; a pulse block enable signal generator for generating a pulse block enable signal; an equalizer signal generator for generating an equalizer signal; a column predecoder for predecoding the column address applied from the column address buffer unit; a column decoder unit for decoding the data input from the column predecoder to select the bit line of the memory cell array; a precharge/equalizer unit for precharging and equalizing the data line according to the output of the equalizer signal generator; and a data I/O buffer unit.