REGRESH ADDRESS TESTING CIRCUIT OF MEMORY CHIP

摘要

A number of adress test paths respectively include a first sub-path with an initial logic level of the refresh address signal and a second sub-path of reflesh address signal. Comparators respectively receive the initial logic level of the signal from the first sub-path and a present logic level of the refresh address signal from the second sub-path. A test output circuit receives output signals generated from the comparators. The circuit verifies self-refresh cycle time.