| 摘要 |
PURPOSE: To provide a clock synchronizing circuit which can accurately adjust the phase of a clock signal used for sampling teletext data so that the phase may have the optimum phasic relation with a teletext data line. CONSTITUTION: Teletext signals are supplied to one input of an XOR gate 9 and a clock signal having a frequency which is equal to a half of that of the teletext signals is supplied to the other input of the gate 9. The output of the gate 9 is supplied to an accumulator 10 in the cycle of a fixed number of teletext signals and a value accumulated in the accumulator 10 is supplied to a clock generator 4. The accumulated value is used for changing the phase of a signal to be used for sampling the teletext signals with respect to the phase of the teletext signals. |
