发明名称 PHASE SYNCHRONIZATION CIRCUIT FOR PRML
摘要 PURPOSE:To prevent steady phase error from occurring due to operation error by easily eliminating error with a loop filter since no terms correlated to the operation error are included in a phase error operation. CONSTITUTION:Sample signals Y2m, Y2(m-1), and Y2m-1 are output at a same timing from a sample hold and distributor 1 for each two symbols. When three- value criterion output slgnals of a three-value criterion circuit 2-4 are set to X2m, X2(m-1), and X2m-1, Y2m-1X2(m-1), Y2m-1XX2(m-1), and (Y2m-Y2(m-1))XX2m-1 are output from a multiplier 7, the second multiplier 7, and a multiplier 8, respectively. Then, tau2m is output from a second subtractor 9 as shown by an expression I. In this case, an operation error as shown by an expression II occurs at a change point due to the delay according to three-value criterion. Since the operation error does not have correlated terms, it can be eliminated by a loop filter 10, thus preventing steady phase error from occurring.
申请公布号 JPH07220406(A) 申请公布日期 1995.08.18
申请号 JP19940013272 申请日期 1994.02.07
申请人 FUJITSU LTD 发明人 SHIMODA KANEYASU
分类号 G11B20/14;H03L7/06 主分类号 G11B20/14
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