发明名称 |
FORMATION OF GATE STACK OF INTEGRATED CIRCUIT |
摘要 |
PURPOSE: To provide a method for forming an integrated circuit whose gate stack structure has a reduced height. CONSTITUTION: A mask layer made of silicon dioxide is removed to leave only a metal layer and a polysilicon layer 30 on a final gate stack 32. It is because the polysilicon layer 30 is used for protecting a field oxide layer from an etchant for selectively removing a hard mask made of oxide that the hard mask made of oxide used for patterning the metal layer can be removed. A polysilicon layer 30 is etched to a gate oxide 12 by using a patterned metal layer 28 as a mask, but the field oxide layer 14 is not thinned.
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申请公布号 |
JPH07221193(A) |
申请公布日期 |
1995.08.18 |
申请号 |
JP19950013270 |
申请日期 |
1995.01.04 |
申请人 |
AMERICAN TELEPH & TELEGR CO <ATT> |
发明人 |
CHIYOONGUUPINGU CHIYANGU;KUOOFUA RII;CHIYUNNTEINGU RIU;RUICHIEN RIU |
分类号 |
H01L21/8234;H01L21/28;H01L27/088;(IPC1-7):H01L21/823 |
主分类号 |
H01L21/8234 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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