| 摘要 |
PURPOSE: To improve the transmission speed and to suppress the occurrence of errors by obtaining a synchronizing signal by matching the phases of the outputs of a plurality of oscillators adjusted to a reference signal in accordance with a prescribed transition. CONSTITUTION: In the clock recovering circuit 30 of a synchronizing signal generating device, two gated voltage-controlled oscillators(GVCO) 31 and 32 are alternately enabled by outputs 34a and 34b of a flip flop 34, and synchronously output a synchronizing signal 52a having a desired phase relation with input data 14 through phase locked loops 41 and 42. When no input data exists, the oscillators 31 and 32 obtain the synchronizing signal 52a based on a reference frequency (f). A NOR gate 90 prevents the occurrence of a logical hazard by preventing the logical NORing of the enable signals. In addition, the synchronizing signal 52a is inputted to a data paralleling circuit 50 through the NOR gate 52 and the jitter contained in the input data is removed. Thus, the transmission speed can be increased and, at the same time, the occurrence of data errors can be suppressed by realizing synchronization with a small transition and making any high-speed clock unnecessary for over-sampling. |
